Method and apparatus for reference-less repeater with digital control

ABSTRACT

Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims the benefit of U.S. ProvisionalApplication No. 61/928,840, filed Jan. 17, 2014, which is incorporatedherein by reference in its entirety.

BACKGROUND

1. Field of the Disclosure

The disclosure generally relates to reference-less repeaters, includingtechniques to estimate a wide range of frequencies in a digital signaland propagate frequency information with digital control.

2. Related Art

Reference-less repeaters provide significant advantages over repeatersrequiring external frequency references. Dedicated frequency referencestypically need additional components that require additional power,mounting, board space, and environmental requirements in order tooperate in a stable and effective manner. Schemes to distribute a commonfrequency reference among a variety of circuits to minimize these issuesimpose further shielding and isolation requirements on reference signaldistribution circuits and board traces. Therefore, retiming circuitsthat eliminate the need for external frequency references providesignificant power, layout, and physical isolation advantages.

Current reference-less repeaters typically employ high-power analog-onlysolutions that while having a wide frequency detection range, also havedifficulty adapting to oversampling. Furthermore, analog-onlyreference-less repeaters have difficulty transferring frequencyinformation from one node to another, and adapting to lower data ratestypically used for auto-negotiation. Analog-only retiming circuitstypically employ analog frequency detectors that consume large amountsof power. Digitally controlled reference-less retiming circuits, on theother hand, have a relatively narrow frequency detection range, buttypically consume significantly less power than analog retimingcircuits. Furthermore, digitally controlled reference-less retimingcircuits provide data rate flexibility, particularly at lower datarates. Due to the narrow frequency detection range of digitallycontrolled reference-less retiming circuits, frequency estimation allowsthese circuits to quickly determine the frequency of an input signal,and distribute the frequency information quickly and efficiently.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

Embodiments of the disclosure are described with reference to theaccompanying drawings. In the drawings, like reference numbers indicateidentical or functionally similar elements. Additionally, the left mostdigit(s) of a reference number identifies the drawing in which thereference number first appears.

FIG. 1 illustrates a block diagram of a receiver/transmitter systemaccording to an exemplary embodiment of the present disclosure;

FIG. 2 illustrates a block diagram of an analog phase locked loopcircuit according to an exemplary embodiment of the present disclosure;

FIG. 3A illustrates a block diagram of a digital control circuit for aphase locked loop according to an exemplary embodiment of the presentdisclosure;

FIG. 3B illustrates a block diagram of an edge periodicity circuit for aphase locked loop according to an exemplary embodiment of the presentdisclosure;

FIG. 4 illustrates an edge counting frequency estimation schemeaccording to an exemplary embodiment of the present disclosure;

FIG. 5 illustrates an edge periodicity frequency estimation schemeaccording to an exemplary embodiment of the present disclosure;

FIG. 6 illustrates an edge periodicity histogram according to anexemplary embodiment of the present disclosure;

FIG. 7 is a flowchart of operational steps to estimate the frequency ofa signal using an edge counting scheme and retime a signal using theestimated frequency;

FIG. 8A is a flowchart of operational steps to estimate the frequency ofa signal using an edge periodicity scheme and retime a signal using theestimated frequency;

FIG. 8B is a flowchart of operational steps to estimate the frequency ofa signal using an alternate edge periodicity scheme and retime a signalusing the estimated frequency;

FIG. 9 is a flowchart of operational steps to estimate the frequency ofa signal using a clock data recovery circuit response and retime asignal using the estimated frequency;

FIG. 10 illustrates an example histogram according to an embodiment.

Embodiments of the disclosure will now be described with reference tothe accompanying drawings. In the drawings, like reference numbersgenerally indicate identical, functionally similar, and/or structurallysimilar elements. The drawing in which an element first appears isindicated by the leftmost digit(s) in the reference number.

DETAILED DESCRIPTION OF THE DISCLOSURE

The following Detailed Description refers to accompanying drawings toillustrate exemplary embodiments consistent with the disclosure.References in the Detailed Description to “one exemplary embodiment” “anexemplary embodiment,” “an example exemplary embodiment,” etc., indicatethat the exemplary embodiment described can include a particularfeature, structure, or Characteristic, but every exemplary embodimentcan not necessarily include the particular feature, structure, orcharacteristic. Moreover, such phrases are not necessarily referring tothe same exemplary embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anexemplary embodiment, it is within the knowledge of those skilled in therelevant art(s) to affect such feature, structure, or characteristic inconnection with other exemplary embodiments whether or not explicitlydescribed.

For purposes of this discussion, the term “module” shall be understoodto include at least one of software, firmware, and hardware (such as oneor more circuits, microchips, processors, or devices, or any combinationthereof), and any combination thereof. In addition, it will beunderstood that each module can include one, or more than one, componentwithin an actual device, and each component that forms a part of thedescribed module can function either cooperatively or independently ofany other component forming a part of the module. Conversely, multiplemodules described herein can represent a single component within anactual device. Further, components within a module can be in a singledevice or distributed among multiple devices in a wired or wirelessmanner.

FIG. 1 illustrates a block diagram of a communication system 100including an external transmitter 106, a backplane or cable 115, and arepeater 103 including a receiver 110 and a transmitter 105. Theexternal transmitter 106 generates a signal that is carried over thebackplane or cable 115 and received by the receiver 110 within therepeater 103. The receiver 110 detects the frequency of the signal andpropagates frequency information to the transmitter 105 that repeats thesignal by transmitting the signal using the frequency information.

The receiver 110 includes a peaking filter 122 and a variable gainamplifier (VGA) 130 that together filter and amplify an incoming signalso that a control circuit 151 can estimate the frequency of the incomingsignal. A receive PLL 143 utilizes the estimated frequency from thecontrol circuit 151 to set a frequency of a clock signal provided to aclock data recovery (CDR) circuit 150. In another embodiment, PLL 143 isshared with the transmitter 105 so that either of transmit PLL 152 orreceive PLL 143 can be eliminated. The incoming signal is equalized andthen sliced by slicer and decision feedback equalizer (DFE) 135, and theresulting signal is provided to the CDR circuit 150. Utilizing thesliced and equalized incoming signal and the clock signal from thereceive PLL 143, the CDR updates a sample point (i.e. phase of samplingtime) for the slicer and DFE 135 in a feedback loop. Once the CDR 150determines that an appropriate sample point for the slicer and DFE 135has been established, the CDR 150 sends an indicator to the controlcircuit 151 to propagate the frequency information to the transmitter105. In response to this indicator, control circuit 151 controls slicerand DFE 135 to for and its output to the transmitter 105.

The transmitter 105 includes a First In First Out (FIFO) buffer 117 thatreceives the output of slicer and DFE 135 and that provides the outputto a transmit (TX) Finite Impulse Response (FIR) filter 119 according toa clock signal generated by a transmit PLL 152. A transmit controlcircuit 153 receives frequency information, for example in digitalformat, from the receive control circuit 151 and provides the frequencyinformation to the transmit PLL 152. The transmit PLL 152, utilizing thefrequency information from the transmit control circuit 153, generatesthe clock signal, for example, with a similar frequency of the clocksignal generated with the receive PLL 143. Therefore, the transmit PCS117 can encode the data using a clock signal similar to the clock signalutilized to extract the data in the receiver 110, without requiring theestimation circuitry included in the receiver 110.

FIG. 2 illustrates a block diagram of an analog phase locked loopcircuit 200 that in some embodiments may correspond to the receive PLL143 or transmit PLL 152 illustrated in FIG. 1. The PLL 200 includes aselector 210 that selects between a control circuit input from thecontrol circuit 151 or 153 through a step size reducer 205, or an outputof a phase error detector 230. When the selector 210 selects the controlinput from the control circuit 151 or 153, the control circuit 151 or153 provides a set frequency value to the step size reducer 205. Thestep size reducer 205 implements a state machine that generatesincremental frequency updates in the form of voltage control signalsover time to the low-pass filter (LF) and leaky integrator 215. In thealternative, when the selector 210 selects the output of the phase errordetector 230, the phase error detector 230 determines a phase errorbetween a divided output, through a divider 225, of a VCO 220, andeither of a reference clock 235 or second clock 240. The second clock240 may for example consist of a clock signal from another desiredreceiver or transmitter.

The LPF and leaky integrator 215 receives the control signal from theselector 210 and low pass filters and integrates the control signal. Insome embodiments, the leaky integrator 215 may drift if updates are notprovided within a predefined time-period characteristic of the leakyintegrator 215. The VCO 220 receives the filtered and integrated controlsignal and oscillates to provide a clock signal, that is output forexample to the CDR 150, where the frequency of oscillation is based on avalue of the control signal. The oscillating frequency of the VCO 220may be coarse tuned based on selecting from one or more capacitor banks222 within the VCO 220. The VCO 220 may be fine-tuned by using thecontrol signal to tune a varactor 221 within the VCO 220. As such, theclock signal generated by the PLL can be updated and maintained throughthe control circuit 151 or 152, or through phase error detection of aprovided reference clock 235 or second clock 240.

FIG. 3A illustrates a block diagram of a control circuit 300 for a phaselocked loop. The control circuit 300 may be one embodiment of thereceive control circuit 151 or the transmit control circuit 152 ofFIG. 1. In some embodiments, the control circuit 300 may control thephase locked loop 143 and 152 of FIG. 1 and the phase locked loop 200 ofFIG. 2.

The control circuit 300 includes a selector 340 that selects betweenfour frequency estimation circuits, an edge counter circuit 330, an edgeperiodicity circuit 331, a CDR response circuit 335, and a frequencycomparator circuit 336. The estimated frequency selected by the selector340 is combined in a signal combiner 340 with an offset generated by anoffset frequency generator 350 that generates frequency offsets tocancel leakiness, for example, in the leaky integrator 215 of FIG. 2. Anoise shaping delta sigma modulator (DSM) 310 uses the offset frequencyestimate and generates a frequency control signal used, for example, bythe receive PLL 143 of FIG. 1 or the PLL 200 of FIG. 2.

The edge counter circuit 330 implements a frequency estimation schemeillustrated and described in FIG. 4, to estimate the frequency of anincoming signal, for example at the output of the VGA 130 of FIG. 1. Theedge counter circuit 330 includes logic to estimate the frequency of thesignal by counting a number of transitions within a given time periodbased on a priori knowledge of the transition density of the signal(e.g., is near 50 percent or other value). The transition density of asignal in a given time period is the ratio of the number transitions (oredges) to the number of bit intervals within the time period.

The edge periodicity circuit 331 implements a frequency estimationscheme illustrated and described in FIGS. 5 and 6, to estimate thefrequency of the incoming signal, for example at the output of the VGA130 of FIG. 1. Briefly, the edge periodicity circuit 331 estimates thefrequency of the signal by determining relationships between the timeperiods between transitions of the input signal. The CDR responsecircuit 335 uses an indication from the CDR circuit 150 that representshow close the frequency of the PLL is to the desired sample point of theslicer 135, and varies the frequency in a searching pattern until adesired sample point is reach. The frequency comparator circuit 336receives, for example, a clock from a local PLL and a clock from anotherPLL to generate the correct desired frequency, for example based on adesired offset between a receive and transmit PLL.

FIG. 3B further illustrates one embodiment of the edge periodicitycircuit 331. Referring to FIG. 3B, the edge periodicity circuit 331 caninclude an edge detector 360, processor and/or logic 362, and anoptional memory 364. The edge detector 360 detects edge transitions andthe corresponding time periods between the edge transitions of the inputsignal. For example, assuming the input signal is a data stream as willbe illustrated below, the edge detector 360 may detect adjacent risingedge transitions or adjacent falling edge transitions, and thecorresponding edge-to-edge time periods between edge transitions, wherethe corresponding time periods may be stored in a corresponding memory364. As will be discussed in detail below, the processor 362 candetermine a “unit time period” by analyzing the plurality ofedge-to-edge time periods of the data stream. After which, thecharacteristic frequency of the data stream can be determined byinverting the unit time period.

FIG. 4 illustrates an edge counting frequency estimation scheme 400 fora signal having a high state 410 and low state 415. The signaltransitions from the low state 415 to the high state 410, for example attime periods 420, 424, and 428. These transitions occur within timeperiod 430. By counting the number of transitions within time period430, for example in the edge counter circuit 330 of FIG. 3, thefrequency of the signal is estimated by dividing the number oftransitions by the time period 430. In some embodiments, the rising edgetransitions from the low state 415 to the high state 410 are counted. Inanother embodiment, the falling edge transitions from the high state 410to the low state 415 are counted and divided by the time period 430. Inanother embodiment, the total number of transitions between the highstate 410 and low state 415 are measured over the time period 430.Embodiments employing this edge counting scheme depend on the transitiondensity between the high state 410 and low state 415 averagingapproximately 50 percent.

FIG. 5 illustrates an edge periodicity frequency estimation scheme 500to estimate the frequency of a signal that transitions between a highstate 510 and a low state 515 of a data stream 505. The signaltransition density between the high state 510 and low state 515 may varybetween 30 percent and 70 percent, resulting in a wider transitiondensity range when compared to that of FIG. 4. In unscrambled dataprotocols, consecutive finite strings of “1” or “0” can occur in thedata stream 505 at different proportions, making it challenging todetect the underlying frequency of the data stream.

Accordingly, the edge periodicity circuit 331 of FIG. 3 measures theeffective time periods between edges of the data stream 505. In anembodiment, edge periodicity circuit 331 uses a clock having a frequencythat is in the vicinity of the frequency of data stream 505 in makingthe measurements. For example, the edge periodicity circuit 331 of FIG.3 detects first time period 520 between the first rising edge and thefirst falling edge in the data stream 505. Likewise, the edgeperiodicity circuit 331 detects a second time period 525 of between thefirst falling edge and the second rising edge, a third time period 520 bbetween the second rising edge and the second falling edge, and a fourthtime period 535 between the second falling edge and the third risingedge, and so on. Due to the periodic nature of the data signal, thediffering time periods are a multiple of a shortest time period, hereinknown as a “unit time period” or “1T” for short, which happens to beequal to time period 520 in data stream 505. Accordingly, the varioustime periods identified between edge-to-edge transitions may be referredto as 1T, 2T, 3T, etc., where “1T” is the unit time period, and theothers are multiples of the unit time period. Once the unit time periodis determined for the data stream, then the underlying frequency of thedata signal can be determined. As described further below, the number ofinstances of the various edge-to-edge time periods in the data signal505 are counted and cataloged so that the unit time period can berecognized.

An alternate method exploits the fact that edge timing is at multiplesof “1T”, using analysis through a narrowband band pass filter tuned tothe frequency of 1/T, which produces a tone at observed input datafrequency. This tone may be used in an edge counter to count virtualtransitions (input data bit times) in an observation interval determinedby the local clock. It may also be shifted in frequency to create anerror function for use in a closed adaptive loop. For example, as shownin FIG. 3B, a filter 366 may be placed at the output of edge detector360. The output of filter 366 may be provided to processor 362, whichcomputes a number of virtual transitions in an observation intervalbased on a local clock that is configured to be near the input datasignal frequency.

FIG. 6 illustrates an edge periodicity histogram, in accordance with thescheme illustrated in FIG. 5. The histogram 600 illustrates the numberof instances 610 of the various edge-to-edge time periods (e.g. 1T, 2T,3T, 4T, etc.) from FIG. 5. Specifically, the histogram includes: thenumber of instances occurring at a unit time period 620 (e.g. “1T”), thenumber of instances occurring at twice the unit time period 625(e.g.“2T”), the number of instances occurring at three times the unittime period 630 (e.g.“3T”), and the number of instances occurring atfour times the unit time period 635 (e.g. “4T”). The histogram is thenanalyzed to determine that all the various time periods are a multipleof a unit time period “1 T”, such that the peaks of the histogram occurat 1T, 2T=(2×1T), 3T=(3×1T), 4T=(4×1T), etc. Stated another way, onceall the various edge-to-edge time periods are accounted for in the datastream 505 and the histogram is formed, the corresponding “peaks” of thehistogram 600 are located at multiples of the “unit time period.” Theinformation contained in the histogram is used to estimate the unit timeperiod “1T” relative to the local clock.

Still referring to FIG. 6, the peaks of the histogram 600 can beunderstood to represent groupings of the individual edge-to-edge timeperiods, so that groups or subsets of the individual edge-to-edge timeperiods have a representative time period centered at the peaks of thehistogram, (e.g. 1T, 2T, 3T, etc.) For example, the group of individualedge-to-edge time periods around “1T” in the histogram can be understoodto be represented by “1T”, the group of individual edge-to-edge timeperiods around “2T” can be understood to be represented by “2T”, and soon. The reasons for the “spread” of individual edge-to-edge time periodsaround their corresponding representative time period (e.g. “1T”, “2T”,etc.) can be caused by channel noise, delay spread, measurementtolerance, among others. Each observation may be grouped to the nearestexpected delay multiple. The edges counted with larger delays can bescaled by the delay multiple to account for missing transitions andsummed. This provides an estimate of the “virtual transitions” orequivalently the number of bit times in the measurement interval, whichcorresponds to the frequency of the input signal relative to the localclocks.

In FIG. 7, the flowchart 700 includes step 705, wherein, the edgecounter 330 counts the number of transitions or virtual transitions in afixed time period to estimate the frequency of an input signal. Based onthe estimated frequency at step 705, the control circuit 151 selects acapacitor bank 222 of FIG. 2 to coarse tune the frequency of the clocksignal generated by the VCO 220. Furthermore, at step 720, the controlcircuit 151 generates an estimated frequency that causes the VCO 220 tofine tune the VCO by modulating a control signal of the varactor 221. Atstep 730, the fine tuned frequency from step 720 is propagated to a TXPLL 152 through a transmit control circuit 153, for example, to tune theTX PLL 152 more quickly with higher precision than would occur withoutthe fine-tuned frequency information.

FIG. 8A provides a flowchart 800 that further describes frequencyestimation and VCO tuning according to one embodiment of the disclosure.Flowchart 800 begins in step 815, which includes, in an embodiment, theedge periodicity circuit 331 of FIG. 3 counting a number of virtualtransitions in an incoming data signal in a predetermined time interval.Virtual transitions as used herein may correspond to time instanceswithin the data signal at which one bit ends and a subsequent adjacentbit begins. A logic transition may or may not occur at these timeinstances, thus the naming as “virtual transitions.” Since each virtualtransition necessarily follows an input data bit time period, the numberof virtual transitions and the number of input data bit times within apredetermined time interval are the same.

At step 820, in an embodiment, the edge periodicity circuit 331 dividesthe predetermined time interval by the number of virtual transitionscounted in step 815 to determine a unit time period. In an embodiment,the unit time period is an estimate of the input data bit time period.Then, at step 825, the edge periodicity circuit 331 inverts the unittime period to estimate a frequency of the incoming data signal.

At step 830, the control circuit 151 selects the VCO capacitor bankbased on the frequency estimation to coarse tune the VCO. The edgeperiodicity circuit 331 fine tunes the VCO by modulating the varactor ofthe VCO based on the frequency estimation at step 835. The controlcircuit 151 propagates the estimated frequency to the transmit I′LL atstep 840 to tune the transmit PLL.

FIG. 8B provides a flowchart 850 that further describes frequencyestimation and VCO tuning according to one embodiment of the disclosure.Flowchart 850 provides an alternate, but related, description offrequency estimation when compared to flowchart 800, and further refersto the elements in FIG. 3B.

In step 850, the edge detector 360 detects a number of edge-to-edge datatransitions in an incoming data stream within a predetermined timeinterval, and determines the corresponding time periods between thedetected edge-to-edge data transitions, which can be stored in anoptional memory 364. Due to the periodic nature of the underlyingfrequency or clock of the incoming data stream, a finite number ofdifferent edge-to-edge transition time periods will result, where eachedge-to-edge transition time period can be represented as a “unit timeperiod,” or an integer multiple of the unit time period. For example,referring to FIG. 5, the edge detector 360 detects the edge-to-edge datatransitions within the shown predetermined time interval and thendetermines their corresponding time periods 520, 525, 520 b, 535, 520 c,550, and 520 d.

At step 855, the processor 362 categorizes the time periods into aplurality of representative groups, each group having a representativetime period that is an integer multiple of a sampling unit time period.The sampling unit time period is the period of a sampling clock at whichrate the incoming data stream is sampled. The sampling clock is relatedto a local clock of the receiver. For example, the sampling clock can beequal to or a multiple of the local clock (e.g., 10 times the localclock). In an embodiment, the local clock can be initially configured tobe near the frequency of the incoming data stream (e.g., within 5-10%).FIG. 10 illustrates an example histogram 1000 that can be generated instep 855 following the categorization of the time periods. Specifically,example histogram 1000 is generated using a sampling clock that is setto 10 times the local clock in order to oversample the incoming datastream. The determined time periods between detected edge-to-edgetransitions form several groups centered at respective multiples of thesampling clock period. For example, the first group centered around thevalue “10” corresponds to edge-to-edge transitions that areapproximately 10 times the sampling clock period apart from each other(or one time the local clock period) (with reference to FIG. 5, thefirst group may include time periods 520, 520 b, 520 c, and 520 d); thesecond group centered around the value “20” corresponds to edge-to-edgetransitions that are approximately twenty times the sampling clockperiod apart (or two times the local clock period) (with reference toFIG. 5, the second group may include time period 525); and so on. It isnoted that if the local clock as configured is slow compared to theincoming data stream, then adjacent groups of time periods in histogram1000 would appear closer to each other than 10 times the sampling clockperiod. Conversely, if the local clock as configured is fast compared tothe incoming data stream, then adjacent groups of time periods inhistogram 1000 would appear farther from each other than 10 times thesampling clock period, as shown in histogram 1000.

At step 860, the processor 362 determines a number of virtualtransitions in the predetermined time interval based on the categorizedtime periods. In an embodiment, the processor 362 determines arespective count for each group of time periods, which corresponds tothe number of time periods within the group. With reference to FIG. 5,the first group (corresponding to 1 local clock period) would receive acount equal to 4, and the second, third, and fourth groups(corresponding to 2 times, 3 times, and 4 times the local clock periodrespectively) would receive a count equal to 1 each. The processor 362then multiplies the respective count of each group by its representativetime period to generate a weighted count. For example, the processor 362counts the number of time periods associated with the group centeredaround the value “10” in example histogram 1000 and then multiples thiscount by “1” because this group corresponds to time periods that areapproximately equal to one local clock period. The processor 362 repeatsthis process for each group of example histogram 1000. The processor 362determines the number of virtual transitions as the sum of all of theweighted counts. For example, with reference to FIG. 5, the processor362 would determine the number of virtual transitions as the sum of4*1+1*2+1*3+1*4, which is equal to 13.

Subsequently, in step 865, the processor 362 divides the predeterminedtime interval by the number of virtual transitions within thepredetermined time interval to determine a unit time period. Forexample, with reference to FIG. 5, assume that the actual unit timeperiod T is equal to 1 msec (i.e., the signal has 1 KHz frequency) andthat the predetermined time interval accordingly is 15 msec long. Theunit time period determined in step 865 would thus equal 1.5 msecdivided by 13 or 1.15 msec. As would be understood by a person of skillin the art based on the teachings herein, in practice the predeterminedtime interval is selected to be significantly longer than the actualunit time period T so that the unit time period estimate converges tothe actual unit time period.

At step 870, the processor 362 inverts the unit time period to determinea frequency estimate of the data stream.

At step 875, the control circuit. 151 selects the VCO capacitor bankbased on the frequency estimation to coarse tune the VCO. The edgeperiodicity circuit 331 fine tunes the VCO by modulating the varactor ofthe VCO based on the frequency estimation at step 880. The controlcircuit 151 propagates the frequency estimate of the incoming datastream to the transmit PLL at step 885 to tune the transmit PLL.

FIG. 9 provides a flowchart 900 that further describes frequencyestimation and VCO tuning according to one embodiment of the disclosure.The flowchart 900 includes step 905, wherein the receive control circuit151 sweeps the receive PLL 143 in coarse steps, and the response of theCDR 150 of FIG. 1, is measured in the CDR response circuit 335 to detecta response and estimate the frequency of the incoming signal. When, forexample, the CDR response circuit 335 detects a response from the CDR,the receive control circuit 151 at step 910 selects the VCO capacitorbank corresponding to the estimated frequency. Likewise, the RX PLL isfine-tuned by modulating an input signal of a varactor of VCO using theresponse of the CDR measured by the CDR response circuit 335. TypicalCDRs have weak responses when the frequency error is large, so thistechnique needs to employ a search algorithm with a fine resolution andis aided by prior methods first arrive near the correct frequency. Theestimated frequency of step 920, at step 930 is propagated to the TX PLLto tune the TX PLL more quickly with higher precision than would occurwithout the fine tuned frequency information.

It is to be appreciated that the Detailed Description section, and notthe Summary and Abstract sections, is intended to be used to interpretthe claims. The Summary and Abstract sections may set forth one or morebut not all exemplary embodiments of the present disclosure ascontemplated by the inventor(s), and thus, are not intended to limit thepresent disclosure and the appended claims in any way. The exemplaryembodiments described herein are provided for illustrative purposes, andare not limiting. Other exemplary embodiments are possible, andmodifications may be made to the exemplary embodiments within the spiritand scope of the disclosure.

Embodiments of the disclosure may be implemented in hardware, firmware,software, or any combination thereof. Embodiments of the disclosure mayalso be implemented as instructions stored on a machine-readable medium,which may be read and executed by one or more processors. Amachine-readable medium may include any mechanism for storing ortransmitting information in a form readable by a machine (e.g., acomputing device). For example, a machine-readable medium may includeread only memory (ROM); random access memory (RAM); magnetic diskstorage media; optical storage media; flash memory devices; electrical,optical, acoustical or other forms of storage devices. Further,firmware, software, routines, instructions may be described herein asperforming certain actions. However, it should be appreciated that suchdescriptions are merely for convenience and that such actions in factresult from computing devices, processors, controllers, or other devicesexecuting the firmware, software, routines, instructions, etc.

The disclosure has been described above with the aid of functionalbuilding blocks illustrating the implementation of specified functionsand relationships thereof. The boundaries of these functional buildingblocks have been arbitrarily defined herein for the convenience of thedescription. Alternate boundaries may be defined so long as thespecified functions and relationships thereof are appropriatelyperformed. It will be apparent to those skilled in the relevant art(s)that various changes in form and detail can be made therein withoutdeparting from the spirit and scope of the disclosure.

What is claimed is:
 1. A frequency estimation circuit, comprising: anedge detector configured to measure time periods between edge-to-edgetransitions in a data stream within a predetermined time interval,resulting in a plurality of edge-to-edge time periods; and a processorconfigured to: categorize the plurality of edge-to-edge time periodsinto a plurality of representative groups, each representative grouphaving a representative time period that is an integer multiple of asampling unit time period; determine a number of virtual transitions inthe predetermined time interval based on the categorized plurality ofedge-to-edge time periods; and determine a frequency estimate of thedata stream based on the number of virtual transitions in thepredetermined time interval.
 2. The frequency estimation circuit ofclaim 1, wherein the edge-to-edge transitions are rising edgetransitions.
 3. The frequency estimation circuit of claim 1, wherein theedge-to-edge transitions are falling edge transitions.
 4. The frequencyestimation circuit of claim 1, wherein the processor is furtherconfigured to: divide the predetermined time interval by the number ofvirtual transitions to determine a unit time period; and invert the unittime period to determine the frequency estimate of the data stream. 5.The frequency estimation circuit of claim 1, wherein the processor isfurther configured to: determine a respective count for a representativegroup of the plurality of representative groups, the respective countcorresponding to a number of edge-to-edge time periods associated withthe representative group; and multiply the respective count by therepresentative time period of the representative group to generate arespective weighted count for the representative group.
 6. The frequencyestimation circuit of claim 5, wherein the processor is furtherconfigured to generate a respective weighted count for each of theremaining ones of the plurality of representative groups.
 7. Thefrequency estimation circuit of claim 6, wherein the processor isfurther configured to determine the number of transitions as a sum ofthe respective weighted counts of the plurality of representativegroups.
 8. A frequency estimation circuit, comprising: an edge detectorconfigured to measure time periods between edge-to-edge transitions in adata stream, resulting in a plurality of edge-to-edge time periods thatare stored in a memory; and a processor, coupled to the memory,configured to: categorize the plurality of edge-to-edge time periodsinto a plurality of representative groups, each representative grouphaving a representative time period; determine a unit time period basedon the representative time periods of the plurality of representativegroups; and invert the unit time period to determine a frequency of thedata stream.
 9. The frequency estimation circuit of claim 8, wherein theunit time period corresponds to a shortest time period among therepresentative time periods of the plurality of representative groups.10. The frequency estimation circuit of claim 8, wherein therepresentative time period of each representative group is an integermultiple of a period of a sampling clock.
 11. The frequency estimationcircuit of claim 8, wherein the edge detector is configured to measurethe time periods between edge-to-edge transitions relative to thesampling clock.
 12. A communications device, comprising: a receivercomprising: a frequency estimation circuit, configured to: count anumber of edge-to-edge transitions in an input data stream in apredetermined time period; and divide the number of edge-to-edgetransitions by a number of bit intervals within the predetermined timeperiod to determine a frequency estimate of the input data stream; areceive voltage controlled oscillator, configured to coarse tune areceive oscillator signal based on the frequency estimate; a slicerconfigured to sample the input data stream based on a slicer inputclock, and provide slicer output data; and a clock and data recoverymodule configured to generate the slicer input clock based on thereceive local oscillator signal and the slicer output data.
 13. Thecommunications device of claim 12, wherein the clock and data recoverymodule is further configured to adjust a sample time of the slicer basedon the slicer output data.
 14. The communications device of claim 12,wherein the frequency estimation circuit estimates the number of bitintervals within the predetermined time period based on a prioriknowledge of a transition density of the input data stream.
 15. Thecommunications device of claim 12, further comprising a transmit circuitthat is coupled to the receiver, and configured to regenerate sampleoutput data from the slicer output data, and transmit the sample outputdata over an associated communications link.
 16. The communicationsdevice of claim 15, wherein the transmit circuit comprises: a transmitvoltage controlled oscillator configured to provide a transmitoscillator signal to clock the regeneration of the sample output data;and a control circuit, configured to receive the frequency estimate fromthe receiver and tune the transmit oscillator signal based on thefrequency estimate.
 17. The communications device of claim 12, whereinthe receive voltage controlled oscillator includes a capacitor bank anda varactor diode, wherein the capacitor bank is used to coarse tune thereceive oscillator signal based on the frequency estimate of the inputdata stream.
 18. The communications device of claim 17, wherein thereceive voltage controlled oscillator forms part of a phase lock loop,the phase lock loop comprising: a phase detector configured to compare aphase of the receive oscillator signal with that of a reference signaland generate a control signal based on the comparison, wherein thecontrol signal is used to fine tune the varactor diode of the receivevoltage controlled oscillator.
 19. The communications device of claim12, wherein the edge-to-edge transitions are rising edge transitions.20. The communications device of claim 12, wherein the edge-to-edgetransitions are failing edge transitions.